1. Field of the Invention
The present invention relates to a power supply used for performing arc-machining operations such as arc welding, arc cutting and plasma arc-machining. In particular, it relates to an arch-machining power supply that can reduce switching loss incurred when direct current is converted to high-frequency alternating current by a switching device.
2. Description of the Related Art
FIG. 1 of the accompanying drawings is a circuit diagram illustrating a conventional power supply used for performing the arc-machining of an object 2 with a torch 1. The sign DR1 refers to a primary rectifier for converting the output from the commercial power source (AC) to direct current. The sign C1 refers to a capacitor for smoothing the voltage of the converted direct current. The combination of the primary rectifier DR1 and the smoothing capacitor C1 provides the DC power source of the illustrated system.
The conventional power supply system includes an inverter provided by the bridge connection of first to fourth switching elements TR1˜TR4. The first and the fourth elements TR1, TR4 make a first switching pair, while the second and the third elements TR2, TR3 make a second switching pair. For conversion of the direct current to the high-frequency alternating current, the first and the second switching pairs are alternately turned on and off in accordance with the first to fourth driving signals Tr1˜Tr4 supplied from a switch driver, or inverter driver SD.
When the switching elements TR1˜TR4 are changed from the on-state to the off-state, a high voltage (surge) of the polarity reverse to that of the elements TR1˜TR4 may occur. To protect the elements TR1˜TR4 from the surge, four diodes DR3˜DR6 are connected in parallel to bypass the elements TR1˜TR4. A main transformer INT, connected to the inverter, is provided for changing the primary voltage to a secondary voltage suitable for arc-machining. The secondary coil of the transformer INT is connected to a secondary rectifier DR2 that converts the AC output of the transformer INT to direct voltage for the arc-machining. This voltage is supplied via a direct current reactor DCL.
An output current detector ID outputs an output current detection signal Id. A comparison operator ER compares this detection signal Id with an output current setup signal Ir, and produces a comparison signal Er=Ir−Id. An output controller SC performs PWM (pulse width modulation) control, in which the frequency of the pulse remains the same, while the width of the pulse is varied. Specifically, based on the comparison signal Er, the output controller SC controls the pulse width of a first output control signal Sc1 (see Sc1 in FIG. 2) and that of a second output control signal Sc2 (see Sc2 in the same figure).
The switch driver SD outputs first and fourth driving signals Tr1, Tr4, both of which are identical, based on the first output control signal Sc1, and also outputs second and third driving signals Tr2, Tr3, both of which are identical, based on the second output control signal Sc2.
FIG. 2 is a timing chart showing the relationships among the first output control signal Sc1, the second output control signal Sc2, the first driving signal Tr1 (which is the same as the fourth driving signal Tr4), the second driving signal Tr2 (which is the same as the third driving signal Tr3), the superposed collector-emitter voltage V1 (solid lines) & collector current Ic1 (broken lines) of the first switching element TR1, and the superposed collector-emitter voltage V2 (solid lines) & collector current Ic2 (broken lines) of the second switching element TR2.
The workings of the first and the second switching elements TR1, TR2 will now be described. It should be noted that the third and the fourth switching elements TR3 and TR4 behave in the same manner as the first and the second switching elements, and therefore they will not be discussed below.
First, the startup switch TS shown in FIG. 1 outputs a startup signal Ts to the output controller SC. Upon receiving the signal, the controller SC outputs the first output control signal Sc1 and the second output control signal Sc2 shifted half cycle relative to the first output control signal Sc1. As shown in FIG. 2, the first and the second output control signals Sc1, Sc2 have pulse durations T1 and T2, respectively, that are determined by the comparison signal Er (=Ir−Id).
In general, the switching elements will take a relatively long time to change from the on-state to the off-state than from the off-state to the on-state. Due to this, without taking any countermeasures, the turn-on states of the first and the second switching pairs would overlap, whereby “arm short-circuiting” occurs. To prevent this, there is an appropriate pause T7 (see FIG. 2) between the on-state of the drive signal Tr1 and the on-state of the drive signal Tr2.
At t=t1, the switch driver SD outputs the first drive signal Tr1 and the fourth drive signal Tr4. Upon receiving this, the first and the fourth elements TR1, TR4 change from the off-state to the on-state. At this time, a switching loss (called “turn-on loss” below) occurs, as represented by the region Ln1 in FIG. 2.
At t=t2 (FIG. 2), the switch driver SD, in synchronism with the first output control signal Sc1, turns off the first and the fourth drive signals Tr1, Tr4. Accordingly, the first and the fourth elements TR1, TR4 change from the on-state to the off-state, which results in the switching loss, or “turn-off loss”, as shown by the region Lf1. In addition to this, saturation loss (not shown) will occur when the first and the fourth elements TR1, TR4 are operating in the saturation region during the on-period T3.
When the above-mentioned pause T7 expires, the first and the fourth elements TR1, TR4, for example, change from the on-state to the off-state, while the second and the third elements TR2, TR3 have already been in the off-state. Thus, a surge voltage will occur across the emitter and the collector of the first and the fourth elements TR1, TR4. The surge voltage is conducted through the bypassing diodes DR3˜DR6, to be absorbed by the smoothing capacitor C1.
The turn-off loss will now be described. During the transition period from the on-state to the off-state, the first and the fourth elements TR1, TR4 are unsaturated. At this time, the collector current Ic1 of the first element TR1 (and that of the fourth element TR4) reduces than when the element is saturated, while the collector-emitter voltage V1 of the element TR1 (and that of the element TR4) increase. The turn-off loss is determined by the product of the collector current Ic1 and the collector-emitter voltage V1 (see the region Lf1 in FIG. 2). If IGBTs (Insulated Gate Bipolar Transistors) are used for the first and the fourth elements TR1, TR4, the collector current Ic will become zero rather slowly after the collector-emitter voltage V1 arises. As a result, the turn-off loss becomes greater.
The turn-on loss will now be described. During the transition from the off-state to the on-state, the first and the fourth elements TR1, TR4 (or TR2, TR3) become saturated. Due to this, the collector-emitter voltage V1 of the first element (and that of the fourth element as well) decreases than in the off-state, while the collector current Ic1 of the first element (and that of the fourth element) increases. The product of the collector current Ic1 and the collector-emitter voltage V1 produces the turn-on loss (see the region Ln1 shown in FIG. 2). The turn-on loss is very small in comparison with the turn-off loss, and its effect is negligible.
Next, the saturation loss will be described. When the first and the fourth elements TR1, TR4 are saturated in the on-state, the collector current Ic of the first element TR1 is a rated current, and the collector-emitter voltage V1 is a saturated voltage. Under this condition, a saturation loss occurs, which is determined by the product of the collector current Ic1 and the collector-emitter voltage V1. The saturation voltage depends on the properties of the switching elements and the drive conditions. Further, the saturation less, not affected by the switching frequency, is essentially constant. Thus, the present invention does not address the reduction of the saturation loss.
At t=t3 shown in FIG. 2, the switch driver SD outputs the second drive signal Tr2 and the third drive signal Tr3. Upon receiving the signal, the second element TR2 and the third element TR3 change from the off-state to the on-state. At this time, a switching loss represented by the region Ln2 will occur.
In synchronism with the second output control signal Sc2, the switch driver SD turns off the second and the third drive signals Tr2, Tr3 at t=t4 (FIG. 2). Thus, the second and the third elements TR2, TR3 change from the on-state to the off-state, and a turn-off loss represented by the region Lf2 will occur. In addition, a saturation loss will occur since the second and the third elements TR2, TR3 operate in the saturated region during the on-period T4. The on-periods T3 and T4 are the same in length.
In the conventional inverter circuit, an unduly great switching loss (“turn-off loss”) will occur when the elements TR1˜TR4 change from the on-state to the off-state. When the frequency of the inverter circuit is increased, the number of switching operations per unit time is increased. As a result, the switching loss per unit time becomes greater. This requires a larger cooling device for preventing the overheat of the switching elements TR1˜TR4. Accordingly, the power supply as a whole becomes bigger, which results in increased costs.